1. Field of the Invention
The present invention relates to dynamic type semiconductor memory devices, and particularly relates to a construction and a method for refreshing information in memory cells.
2. Description of the Related Art
In recent years, personal computers have become popular among general users. Particularly, in the most recent years, demand has been increased for the personal computers of a portable type called as a lap-top type. These portable personal computers can be carried to any places, which is one of the features thereof. In view of actual usage, it is preferable to support a battery back-up function therein. The battery back-up function is such a function that data written in an internal memory can be held by a battery, for instance, during carriage thereof.
The portable personal computers have employed as the internal memories DRAM's (dynamic random access memories) or SRAM's (static random access memories). Particularly, the DRAM's which are inexpensive and have large storage capacities have been widely used as the internal memories.
The DRAM stores information by storing charges in a memory capacitor such as a MOS (metal insulator semiconductor) capacitor as shown in FIG. 1.
FIG. 1 schematically illustrates a construction related to a pair of bit lines in the DRAM. In FIG. 1, there is shown a bit line construction of a memory having a "folded bit line" construction as an example.
In FIG. 1, bit lines for having information transmitted thereon comprises a pair of bit lines BL and BL which transmit mutually complementary data. A memory cell M1 is disposed at an intersection between a word line WL1 and the bit line BL, and a memory cell M2 is disposed at an intersection between a word line WL2 and the complementary bit line BL. The memory cell M1 includes a capacitor C1 storing an information in a form of charges and a transfer gate transistor T1 which connects the capacitor C1 to the bit line BL in response to a signal potential on the word line WL1. The memory cell M2 includes a capacitor C2 storing an information in a form of charges and a transfer gate transistor T2 which connects the capacitor C2 to the complementary bit line BL in response to a signal potential on the word line WL2.
The paired bit lines BL and BL are associated with a sense amplifier SA which is responsive to a sense amplifier activating signal .phi. for differentially sensing and amplifying the signal potentials on the bit line pair BL and BL.
Between the bit lines BL and BL and I/O lines I/O and I/O, there are respectively provided I/O gate transistors IG1 and IG2, which are selectively turned on in response to a column selecting signal (column decode signal) Y.
Each of the word lines WL1 and WL2 has connected thereto memory cells of one row. The bit line pair BL and BL has connected thereto memory cells of one column. In operation of the memory, a word line (e.g., WL1) is selected by a row decoder (not shown) in response to an externally applied row address signal. When the word line WL1 is selected, the transfer gate transistor T1 in the memory cell M1 is turned on, and the capacitor C1 is connected to the bit line BL.
Then, the sense amplifier SA is activated at a predetermined timing in response to the sense amplifier activating signal .phi. to differentially sense and amplify the potential difference between the bit lines BL and BL. After the sense amplifier SA completes the sensing operation and the potential on the bit lines BL and BL are sufficiently developed, the I/O gate transistors IG1 and IG2 become conductive in response to the column selecting signal Y from a column decoder (not shown), and thus the bit lines BL and BL are connected to the I/O lines I/O and I/O, respectively. In the data writing operation, a data transmitted through the I/O line I/O is written in this selected memory cell M1.
In the data reading operation, the signal potentials on these I/O lines I/O and I/O are read out, as an output data, through a preamplifier, output buffer and others, all of which are not shown.
As described above, since the DRAM stores the information in the capacitors, the stored charges in the capacitors tend to be gradually discharged due to a leak current. In order to prevent destruction of the stored information through the discharge of the stored charges from the capacitors, periodical restoration of the contents of the memory cells are required for compensating for the discharge of the stored charges caused by the leak current. This operation is called as refresh. In the DRAM, this refresh operation is periodically performed with respect to respective word lines.
This refresh operation is also required for the battery back-up operation in the portable personal computer described above so as to hold the memory contents.
There are several refresh modes of DRAM, such as RAS only refresh mode and CAS before RAS refresh mode.
FIG. 2 illustrates signal waveforms in the RAS only refresh mode. With reference to FIG. 2, the RAS only refresh operation will now be briefly described.
A refresh address counter, which is provided at an exterior of the memory and is controlled by instructions, e.g., from CPU, applies a refresh address to the DRAM. Then, an address Q0-Qn for this refresh is accepted in the memory at a falling edge to "L" of a row address strobe signal RAS. At this time, a column address strobe signal CAS as well as a read/write signal W for controlling read and write of the memory can take arbitrary states. FIG. 2 illustrates an example in which both of them are set at "H". A corresponding word line in the memory is selected by the refresh address Q0-Qn, and the information in the memory cell connected to this selected word line is read to the related bit line. After elapse of a predetermined period of time from the falling edge of the row address strobe signal RAS, the sense amplifier activating signal .phi. rises to activate the sense amplifier SA. Consequently, the information read out from the memory cell is amplified, and the amplified data is written in the same memory cell, i.e., memory cell from which the information has been read out.
In this refresh mode, the column address decode signal is not generated, so that the I/O gate transistors IG1 and IG2 (see FIG. 1) is kept in an off state. As described above, the data amplified by the sense amplifier SA is written in the same memory cell for refreshing the information in the memory cell (in this case, the memory cells connected to one word line).
In this RAS only refresh mode, if the column address strobe signal CAS is set at the active state of "L" after the refresh instruction, and the read/write signal W is set in either the read enable mode or the write enable mode, the operation can immediately turns from the refresh mode into the normal read or write mode.
As the refresh of a DRAM, there have been functions called as self-refresh function and auto-refresh function with the above refresh function supported inclusive in a DRAM.
FIG. 3 is a block diagram illustrating a construction of a refresh circuit in DRAM containing the refresh function with which refresh addresses are internally generated. The refresh circuit shown in FIG. 3 is disclosed in an article "A 64K bit MOS Dynamic RAM with Auto/Self refresh functions" by Yamada et al., Institute of Electronics and Communication Engineers, Transactions (C), Vol. 10-66C, No. 1, January 1983, pp 62-69.
Referring to FIG. 3, the refresh circuit includes a refresh control circuit 101 which generates various control signals in response to an externally applied refresh instruction signal REF, a timer 102 which generates a refresh request signal REFREQ for a predetermined time in response to an activating signal from the refresh control circuit 101, a refresh address counter 103 which generates refresh address signals for designating a row to be refreshed, and a multiplexer 104 which allows selective passage of one of externally applied address signals A0-An and the refresh address signals Q0-Qn in response to switching control signals MUX and MUX from the refresh control circuit 101. The refresh address counter 103 increments its count by "1" in response to a word line clock signal .phi.w from a RAS control circuit 105 described later. The word line clock signal .phi.w provides a timing for setting a word line in the selected state. The potential of the selected word line rises at the timing of this word line clock signal .phi.w.
The refresh circuit also includes the RAS control circuit 105 which generates an internal row address strobe signal Int.RAS for controlling the operations of row selecting circuitry, and a CAS control circuit 106 which generates an internal column address strobe signal Int.CAS for controlling the operations of column selecting circuitry. The RAS control circuit 105 includes at its input a NAND gate 107 for receiving a control signal MUX' from the refresh control circuit 101 and the externally applied row address strobe signal RAS. The CAS control circuit 106 includes at its input a NOR gate 108 for receiving a column selection operation inhibiting signal CASIHT from the refresh control circuit 101 and the column address strobe signal CAS. The RAS control circuit 105 also generates a signal for activating the CAS control circuit 106 in response to the externally applied row address strobe signal RAS.
The address signals from the multiplexer 104 are applied to the address buffer 109. The address buffer 109 in response to the internal row address strobe signal Int.RAS from the RAS control circuit 105 to accept the applied address signals for generating the internal row address signals which in turn are applied to the row address decoder. The operations of the refresh circuit shown in FIG. 3 will be described with reference to FIG. 4 illustrating operation waveforms thereof. This refresh circuit can perform the operations both of the auto-refresh and the self-refresh. FIG. 4 illustrates the operation waveforms in the auto-refresh operation.
When a RAS precharge time t.sub.d (RAS-REF) elapses after the signal RAS rises from "L" to "H" to set the memory in the standby state, the refresh instruction signal REF is allowed to fall from "H" to "L". This RAS precharge time is a time required for precharging the sense amplifier circuitry.
The auto-refresh is started by falling the refresh instruction signal REF from "H" to "L" at a time t0. The refresh control circuit 101, in response to this activated refresh instruction signal REF, sets the switch control signal MUX to "H" and the complementary switch control signal MUX to "L" before a time t1. In response to these switch control signals MUX and MUX, the multiplexer 104 selects the refresh address signals Q0-Qn sent from the refresh address counter 103 and transmits them to the address buffer 109.
After generating these switch control signals MUX and MUX, the refresh control circuit 101 generates a signal MUX', delayed by a predetermined time to the signal MUX and applies it to the NAND gate 107. This control signal MUX' is currently in the active state of "L", so that an output of the NAND gate 107 is "H". In response to the signal at "H" from the NAND gate 107 the RAS control circuit 105 generated the internal row address strobe signal Int.RAS (time t1).
In order to prevent the mutual interference between the externally applied address signals A0-An and the refresh address signals Q0-Qn, it is designed to prevent the switch control signals MUX and MUX from having their "H" level period overlapping with each other (the address signals corresponding to the switch signal at "H" are passed).
The signal MUX' is delayed by the predetermined time relative to the signal MUX for the purpose that the activation time of the address buffer 109 can be surely set at a time after the completion of the multiplexing operation of the multiplexer 104.
The word line clock signal .phi.w is generated at a time t2 with a delay by a predetermined time after the RAS control circuit 105 generates the internal row address strobe signal Int.RAS. Thereby, the word lines designated by the refresh addresses Q0-Qn are set at the selected state.
Then, the word line clock signal .phi.w increments by "1" the count of the refresh address counter 103 (between times t2 and t3).
Meanwhile, upon generation of the refresh instruction signal, the signal CASIHT for inhibiting the column selecting operation is set at "H" by the refresh control circuit 101 and is applied to the NOR gate 108. In this operation, the output of the NOR gate 108 is "L", and the CAS control circuit 106 maintains the internal column address strobe signal Int.CAS at "L". Thereby, the column selection operation is not performed.
At the time t3 after the rising of the word line clock signal .phi.w to "H", the sense amplifier activating signal (signal .phi. in FIG. 1) is generated and thus the sense amplifier is activated. The sense amplifier senses and amplifies the information in a memory cell connected to the selected word line, and storing of the information in the same memory cell, i.e., refresh, is performed.
At a time t4, the refresh end signal REFEND is generated from the RAS control circuit 105 and is applied to the refresh control circuit 101. This refresh end signal REFEND is generated when a predetermined time elapses after the generation of the word line clock signal .phi.w. The refresh control circuit 101 raises the signal MUX', from "L" to "H" in response to this refresh end signal REFEND. In response thereto, the output of the NAND gate 107 changes to "L". Accordingly, the internal row address strobe signal Int.RAS from the RAS control circuit 105 falls from "H" to "L". The sense amplifier circuitry starts to be precharged and is brought to the condition ready for the next memory operation or the refresh operation.
A period of time t.sub.d (REF-RAS) from the termination of the refresh to the start of the normal memory cycle is a period of time required from completion of the precharging of the sense amplifier circuitry to the start of the standby state of the memory.
A period of time t.sub.su (REF-RAS) shown in FIG. 4 is a period of time required from the start of an auto-refresh to the return to a normal memory operation.
In the refresh circuit shown in FIG. 3, when the refresh instruction signal REF is externally applied, the refresh addresses are automatically and internally generated to perform and complete the refresh. This refresh circuit further includes a self-refresh function with which the refresh is automatically and repeatedly performed as long as the signal RAS is "H" and the refresh instruction signal REF is "L". FIG. 5 illustrates an operation waveform in this self-refresh mode. This self-refresh operation will now be described with reference to FIGS. 3 and 5.
As can be understood from the comparison of the operation timing diagram of the auto-refresh shown in FIG. 4 and that of the self-refresh shown in FIG. 5, the auto-refresh and the self-refresh are similar to each other. Difference between them is a hold time Tw (REFL) for holding the refresh instruction signal REF at "L". The self-refresh starts at a time S0 at which the self-refresh instruction signal REF changes from "H" to "L". The internal operation between the times S0 and S1 proceeds in the same manner as that for the auto-refresh. That is, there is no distinction between the auto-refresh and the self-refresh until the time S1.
At the time S1, i.e., upon completion of the first refresh operation, the timer 102 is activated in response to the signal from the refresh control circuit 101. If the refresh instruction signal REF is held at "L" for a period exceeding a set time Tset (usually 12-15 .mu.s) predeterminedly set in the timer 102, a refresh request signal REFREQ is generated by the timer 102 and is applied to the refresh control circuit 101. In response thereto, the refresh operation restarts, and, the refresh is performed for the memory cells which is selected by the refresh address incremented by one bit as compared with that at the time S0. Before a time S3, the refresh address of the refresh address counter 103 is further incremented by one bit.
This operation is repeatedly performed as long as the signal RAS is at "H" and the signal REF is held at "L".
In FIGS. 4 and 5, the word line clock signal .phi.w is once raised to "H" level and subsequently is further raised for the purpose that, after a word line is selected and the sense amplifier is activated, the word line potential may be further raised for ensuring the writing of the level "H" amplified by the sense amplifier in the memory cell. The reason why the output Nst from the timer (see FIG. 5(g)) gradually decreases is that the timer 102 indicates the time by means of a discharge potential of the capacitor.
The self-refresh operation is performed asynchronously to the input of the refresh instruction signal REF. Therefore, at an instant at which the refresh instruction signal REF returns from "L" to "H" for the change from the self-refresh to the normal memory operation, it is impossible to identify the state to which the internal refresh operation has advanced when interrupted. Therefore, while the refresh request signal REFREQ is generated, it is necessary to inhibit the application of the refresh instruction signal REF. Owing to this construction, when the refresh instruction signal REF returns from "L" to "H" at a time between the times S3 and S4, the self-refresh terminates at that time point. If the refresh instruction signal REF returns from "L" to "H" at a time between the times S4 and S5, the termination of the self-refresh is postponed to a time S6 of termination of the refresh operation.
If the self-refresh instruction signal REF returns from "L" to "H" at a time between the times S5 and S6, the termination of the self-refresh is also postponed to the time S6.
As described above, due to asynchronous characteristics of the self-refresh, a period of time for one cycle should be reserved as the period of time t.sub.d (REF-RAS) between the change of the refresh instruction signal REF from "L" to "H" and the subsequent change of the signal RAS from "H" to "L".
As described above, the auto-refresh mode and the self-refresh mode are operation modes for performing only the refresh, and thus, in order to perform the memory operation for a normal writing or reading of the memory, it is necessary to lower the signal RAS to "L" after the setting of the refresh instruction signal REF to "H" and simultaneously to apply address signals from an exterior.
In addition to the constructions for externally applying the refresh instruction signal REF as described above, there is provided an operation mode called as a CAS before RAS refresh using the signals RAS and CAS as the refresh instruction signals. This is an operation mode in which the refresh is designated by the condition in which the external signal CAS is already in the active state of "L" at the time of falling of the external signal RAS.
FIG. 6 illustrates a construction of the refresh instruction signal generating circuit for achieving the CAS before RAS refresh mode. In FIG. 6, this CAS before RAS refresh instruction signal generating circuit includes a CAS before RAS detecting circuit 150 and an instruction signal generating circuit 160 for generating the refresh instruction signal REF in response to an output of the detecting circuit 150.
The CAS before RAS detecting circuit 150 includes NAND gates G1 and G2 as well as inverters G3, G4 and G5. The inverter G3 inverts the externally applied signal RAS and generates an inverted delay signal .phi..sub.R. The inverter G4 inverts the externally applied signal CAS and generates an inverted delay signal .phi..sub.C.
The NAND gate G1 receives the signal .phi..sub.R and an output of the NAND gate G2. The NAND gate G2 receives the signal .phi..sub.C and an output of the NAND gate G1. The inverter G5 inverts the output of the NAND gate G2 and generates the CAS before RAS detecting signal CBR.
The refresh instruction signal generating circuit 160 receives the signal .phi..sub.R from the inverter G3 and the CAS before RAS detecting signal CBR from the inverter G5. Operations thereof will be described with reference to FIGS. 7 and 8 illustrating the operation waveforms thereof. First, referring to FIG. 7, a normal operation cycle for normal read and write of the data will be described.
When both the signals RAS and CAS are "H" and thus the memory (DRAM) is in the standby state, both the signals .phi..sub.R and .phi..sub.C from the inverters G3 and G4 are "L". Therefore, both the outputs from the NAND gates G1 and G2 are "H".
Falling of the signal RAS causes the memory operation to start. In response thereto, the signal .phi..sub.R from the inverter G3 rises to "H". Since the output signal of the NAND gate G2 is currently "H", the output of the NAND gate G1 lowers to "L" in response to the rising of the signal .phi..sub.R. At this time, since the signal CAS is still "H", the signal .phi..sub.C is "L" and the output of the NAND gate G2 is still "H".
When the signal CAS lowers to "L" thereafter, the signal .phi..sub.C from the inverter G4 rises to "H". In this time, since the output of the NAND gate G1 is "L", the output CBR of the NAND gate G2 maintains "H".
When the signals CAS and RAS rise to "H" after the completion of one memory cycle, the respective signals .phi..sub.R and .phi..sub.C lower to "L". In response to the lowering of the signal .phi..sub.R to "L", the potential of the node N1 (i.e., output of the NAND gate G1) rises to "H".
Since the signal RAS normally rises to "H" after the rising of the signal CAS, both the signal .phi..sub.C and the potential of the node N1 do not become "H" at the same time, and thus the output of the NAND gate G2 maintains "H".
Therefore, the output signal CBR of the inverter G5 is fixed to "L" in this normal operation cycle. The NAND gate G6 receives this signal CBR and the signal .phi..sub.R. Since the signal CBR is "L", the refresh instruction signal REF is fixed to "H", and thus the refresh instruction signal is not generated.
Then, the refresh operation will be described with reference to FIG. 8. In the CAS before RAS refresh mode, the signal CAS lowers to "L" prior to the falling of the signal "RAS". In the initial state, i.e., in the standby state, the outputs of the NAND gates G1 and G2 are "H". When the signal CAS lowers to "L", the signal .phi..sub.C rises to "H". Thereby, the output of the NAND gate G2 lowers to "L", and the signal CBR from the inverter G5 rises to "H". In this time, the signal .phi..sub.R is still "L", so that the output signal REF of the NAND gate G6 is still "H".
When the signal RAS lowers to "L" in this condition, the signal .phi..sub.R rises to "H". In response to the rising of the signal .phi..sub.R to "H", the output signal REF of the NAND gate G6 lowers to "L". The refresh instruction is provided by this lowering of the signal REF to "L".
When the signal CAS rises to "H", the signal .phi..sub.C lowers to "L". In response thereto, the output signal CBR of the NAND gate G2 also rises to "H". The signal .phi..sub.R is in the state of "H" because the signal RAS is still "L" at this time.
The signal CBR from the inverter G5 lowers to "L" in response to the rising of the output signal from the NAND gate G2 to "H". Therefore, the output signal REF of the NAND gate G6 rises to "H" in response to the lowering of the signal CBR to "L". This indicates the termination of the refresh.
Thereafter, the signal RAS rises to "H" and the signal .phi..sub.R lowers to "L", whereby one refresh operation is completed.
In this CAS before RAS refresh mode, the refresh cycle period is determined by a period for which the signal CAS is at the "L" level. Therefore, the period for the self-refresh is determined by the period during which the signal CAS is at the "L" level.
The construction of the refresh circuit for the CAS before RAS refresh mode is slightly different from that in FIG. 3, in the point that the NAND gate 107 in FIG. 3 is eliminated and the RAS signal is directly transmitted to the RAS control circuit 105.
Also in this CAS before RAS mode, the operation cycle thereof provides an operation mode performed only for the refresh, and it is necessary to sequentially lower the signals RAS and CAS to "L" in a predetermined order after the change to the standby state and to apply the address, for performing the normal operation cycle again.
In view of reduction of the power consumption of the semiconductor memory device, there has been generally used a semiconductor memory device of a block division type, in which a memory cell array is divided into a plurality of blocks, and only the block related to an applied address among the memory cell blocks is selected to be driven. This construction has been employed in view of a fact that a current caused by the charging and discharging of bit lines during the operation of the sense amplifier bears a considerably high ratio to a total current consumption of DRAM. That is, in the normal operation, only a sense amplifiers which are associated with the memory cells of the block related to the externally applied signal are activated, and the sense amplifiers related to the remaining blocks are maintained in an inactive or standby state, whereby the charge and discharge currents of the bit lines are reduced, resulting in reduction of the total current consumption of the DRAM.
FIG. 9 schematically illustrates a construction of a conventional semiconductor memory device having a memory capacity of 1 Mbits. Referring to FIG. 9, a memory cell array 1 is divided into 8 memory cell blocks MA1-MA8. Each of the memory cell blocks MA1-MA8 includes memory cells disposed in 256 rows by 512 columns. These memory cell blocks MA1-MA8 are grouped into two groups based on the highest order address bit RA8 of a row address. Specifically, one of the groups includes the memory cell blocks MA1, MA2, MA5 and MA6 having the highest order address bit RA8 of "0" and the other group includes the memory cell blocks MA3, MA4, MA7 and MA8 having the highest order row address bit RA8 of "1".
Sense amplifier groups SA1-SA8 are associated with the memory cell blocks MA1-MA8, respectively. Each of the sense amplifier groups SA1-SA8 includes sense amplifiers which are associated with respective bit line pairs of the corresponding memory cell block and are operable to differentially detect and amplify signal potential differences on the respective bit line pairs.
There are provided column decoders CD1-CD4, each of which is associated with adjacent two memory cell blocks for selecting columns in each associated memory cell block. The column decoder CD1 selects one column in each of the memory cell blocks MA1 and MA2. The column decoder CD2 selects one column in each of the memory cell blocks MA3 and MA4. The column decoder CD3 selects one column in each of the memory cell blocks MA5 and MA6. The column decoder CD4 selects one column in each of the memory cell blocks MA7 and MA8.
A row decoder 2 is provided for selecting a row in the memory cell array 1. The row decoder 2 selects a row in the eight memory cell block MA1-MA8. More specifically, it selects one row in each memory cell block included in either of the two groups according to the highest order row address bit RA8.
An address buffer 3 is provided for applying row address signals and column address signals to the row decoder 2 and the column decoders CD1-CD4, respectively. The address buffer 3 receives externally applied address signals A0-A8 to generate internal address signals RA0-RA8 and internal column address signals CA0-CA8. The row signals and column address signals are applied to the address buffer 3 in a time division multiplexing manner. Timings for latching these row address signals and column address signals are set by the externally applied control signals RAS and CAS.
A sense amplifier activating signal generating circuit 4 is provided for activating only the sense amplifier group which is associated with the memory cell blocks including the word lines selected by the row decoder 2. The sense amplifier activating signal generating circuit 4 activates either the sense amplifier activating signal .phi.0 or .phi.1 in response to an internal control signal Int.RAS generated by a control signal generating circuit 5 and the highest order address bit RA8 from the address buffer 3. When the internal row address signal bit RA8 is "0", the activating signal .phi.0 for the sense amplifier groups SA1, SA2, SA5 and SA6 is activated. When the highest order address signal bit RA8 is "1", the activating signal .phi.0 for activating the sense amplifier groups SA3, SA4, SA7 and SA8 is activated.
In this construction, since the column decoders CD1-CD4 select the data of four columns, i.e., of four bits, there is further provided an I/O buffer circuit 6 having a function for selecting one bit from the data of 4 bits. The I/O buffer circuit 6 responds to the highest order row and column address signal bits RA8 and CA8 for selecting only one bit in the selected four bits to couple that bit with the external of the device.
The control signal generating circuit 5 generates various internal control signals in response to the externally applied signals RAS, CAS and W. In the construction shown in FIG. 9, there is however represented only the internal signal Int.RAS related to the activation of the sense amplifiers.
If the signal W is at "L" and thus indicates the data writing, the I/O circuit 6 transmits an externally applied data to a selected memory cell. If the signal W is at "H" and thus indicates the data reading, one bit data among the selected four bit data is outputted as the output data. The construction for selecting only one bit among the four bits is employed for the semiconductor memory device having a ".times.1" construction. If it has a ".times.4" bit construction, the I/O circuit 6 will operate to give and receive the applied memory cell data of 4 bits to and from the external of the device.
FIG. 10 is a view showing a specific construction of the sense amplifier activating signal generating circuit 4 shown in FIG. 9. In FIG. 10, the sense amplifier activating signal generating circuit 4 includes a delay circuit 10 which delays the internal signal Int.RAS by a predetermined time to generate a sense amplifier drive signal .phi.x, and a multiplexer circuit 11 which uses the highest order row signal bit RA8 to select a transmission path for outputting the sense amplifier drive signal .phi.x from the delay circuit 10.
The multiplexer circuit 11 includes a gate circuit G10 which receives at it false input the highest order row address signal bit RA8 and receives at its true input the sense amplifier drive signal .phi.x, and a gate circuit G11 which receives at its one input the highest order address signal bit RA8 and receives at its other input the sense amplifier drive signal .phi.x. When the highest order row address signal bit RA8 is "0", i.e., if its potential is "L", the gate circuit G10 is enabled, and the sense amplifier activating signal .phi.0 is generated in response to the sense amplifier drive signal .phi.x.
If the highest order row address signal bit RA8 is "1", the gate circuit G11 is enabled, and the sense amplifier activating signal .phi.1 is generated in response to the sense amplifier drive signal .phi.x. Now, operations of the semiconductor memory device shown in FIGS. 9 and 10 will be briefly described with reference to FIG. 11 which is an operation waveform diagram thereof.
In the normal cycle, i.e., for the reading or writing of the data, the externally applied signal RAS first falls to "L". Thereby, the memory cycle starts and the address buffer 3 latches the externally applied address signals A0-A8 as the row address signals and applies them to the row decoder 2. In response to this external signal RAS, the control signal generating circuit 5 generates the internal signal Int.RAS. The internal control signal Int.RAS actives the operation of the row selection circuitry and the row decoder 2 decodes the applied internal row address signals RA0-RA8 to select the rows corresponding to the row address signals. In the construction shown in FIG. 9, one row is selected in each of the four blocks. The data in the memory cells connected to the selected word lines are transmitted to the bit lines. When the potential difference on the bit lines increases to a certain value, then the sense amplifier activating signal generating circuit 4 generates the sense amplifier activating signal .phi.0 or .phi.1, and the minute potential differences on the bit lines are further amplified differentially. After the potentials on the bit lines are settled to be "H" and "L", respectively, the column decoders CD1-CD4 select one column in each block, i.e., select a total of four columns in response to the internal column address CA0-CA8 received from the address buffer 3 and the selected columns are connected to the I/O circuit 6. The I/O circuit 6 selects one column from these selected four columns and connects it to the external of the device. Here, the actually activated column decoder among those CD1-CD4 is a column decoder which is associated with the memory cell block including the selected row.
As described above, the eight memory cell blocks are grouped into two groups, and only the sense amplifier groups corresponding to the memory cell blocks in one group are driven, whereby the charge and discharge current in the sensing operation can be reduced by half as compared with the case in which the sense amplifier groups in all the blocks are driven, resulting in reduction of the current consumption and the reduction of the peak current. The reduction of the peak current can also reduce the amount of current flowing to the substrate in the sensing operation, and thus it is possible to avoid disadvantages such as destruction of the memory cell data, for example, due to generation of holes by impact ionization which may be caused by the substrate current flowing from the power supply line to the substrate and variation of the substrate potential. This ensures more stable operations of the semiconductor memory device.
In the semiconductor memory device with the refresh mode such as the conventional CAS before RAS refresh cycle, the amount of the bit line charge and discharge current in the refresh operation of one cycle is the same as that in the normal operation, and thus, with respect to the peak current and the current consumption, the refresh operation is similar to the normal operation.
As shown in FIG. 12, in the memory system of a computer, a large number of semiconductor memory devices (memory IC's) MIC are arranged on a memory board 50. FIG. 12 illustrates an example in which twelve semiconductor memory devices (memory IC's) MIC are arranged on the memory board 50. The arrangement of the plurality of semiconductor memory devices on the memory board 50 allows a memory system, i.e., address space, to have a large capacity, using the memory cell devices of small capacities. This memory board 50 is connected to a data bus of the computer through a connector 51.
In this memory system, although it depends on the construction of the memory system, a construction of one word with a plurality of bits is achieved by simultaneously reading the data from the plurality of memory IC's in such a case that one semiconductor memory device MIC has a .times.1 bit construction.
Further, in the memory system described above, a memory bank construction is employed in which predetermined number of semiconductor memory devices are used as one bank. Address spaces A, B and C are allotted to each bank, as shown in FIG. 13, and an address space having a large capacity is achieved, using the semiconductor memory devices having substantially small capacities, by selecting the banks correspondingly to the respective address spaces. FIG. 13 illustrates an example in which the semiconductor memory devices MIC1-MIC4 are used for the address space A, the semiconductor memory devices MIC5-MIC8 are used for the address space B, and the semiconductor memory devices MIC9-MIC12 are used for the address space C.
In the memory system described above, a major part of the semiconductor memory devices are in a data hold state, and only a part of the semiconductor memory devices are accessed for reading or writing the data. Therefore, with respect to the peak current in the normal operation, it is necessary to consider the peak current in the semiconductor memory devices which are actually accessed. However, in the refresh operation, all of the memories for the data storage are refreshed simultaneously, so that the peak current in the refresh operation has a value remarkably larger than that in the normal operation, and the current consumption, and particularly peak current, in the refresh operation cause a remarkable problem in the personal computer of the battery back-up type which requires a remarkably low current consumption.
In the personal computers having the battery back-up function and adapted to perform the refresh during the back-up by the battery, and particularly in the personal computers using the semiconductor memory devices with the refresh function, since all of the semiconductor memory devices in the system simultaneously perform the refresh operation, the peak current during the refresh is large and thus the current consumption of the battery is large, which causes remarkable consumption of the battery during the battery back-up, and thus the battery back-up function cannot be sufficiently accomplished.